1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to the manufacture of transistors having strained channel regions by using stress-inducing sources, such as globally strained silicon substrates and the like, in order to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Generally, a plurality of process technologies are currently practiced to fabricate integrated circuits, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is presently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions formed by an interface that is defined by highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode located in close proximity to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the mobility of the charge carriers and the channel length. Hence, the conductivity of the channel region is a dominant factor determining the performance of MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is an important design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith, such as reduced controllability of the channel, also referred to as short channel effects, and the like, that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For instance, the thickness of the gate insulation layer, frequently an oxide-based dielectric, has to be reduced with reducing the gate length, wherein a reduced thickness of the gate dielectric may result in increased leakage currents, thereby posing limitations for oxide-based gate insulation layers at approximately 1-2 nm. Thus, the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques, for example, for compensating for short channel effects with oxide-based gate dielectric scaling being pushed to the limits with respect to tolerable leakage currents. It has, therefore, been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to technology nodes using reduced gate lengths, while avoiding or at least postponing many of the problems encountered with the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region so as to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, creating uniaxial tensile strain in the channel region along the channel length direction for a standard crystallographic orientation increases the mobility of electrons, which in turn may directly translate into a corresponding increase in conductivity. On the other hand, uniaxial compressive strain in the channel region for the same configuration as above may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
In some approaches, external stress, created by, for instance, permanent overlaying layers, spacer elements and the like, is used in an attempt to create a desired strain within the channel region. Although a promising approach, the process of creating the strain in the channel region by applying a specified external stress may depend on the efficiency of the stress transfer mechanism for the external stress provided, for instance, by contact layers, spacers and the like into the channel region to create the desired strain therein. Thus, for different transistor types, differently stressed overlayers have to be provided, which may result in a plurality of additional process steps, wherein, in particular, any additional lithography steps may significantly contribute to the overall production costs, while the resulting strain level may be less than desired, in particular for highly scaled transistors, due to limitations caused by deposition constraints of the highly stressed materials. Hence, the amount of stress-inducing material, and in particular the intrinsic stress thereof, may not be arbitrarily increased without requiring significant design alterations.
In other approaches, a strain-inducing semiconductor alloy may be provided within drain and source regions, which may exert a specified type of stress on the channel region to thereby induce a desired type of strain therein. For example, a silicon/germanium alloy may frequently be used for this purpose in order to obtain a compressive stress component in the adjacent channel region of, for instance, P-channel transistors in order to increase mobility of holes in the corresponding P-channel. In sophisticated applications, two or more of the above-specified strain-inducing mechanisms may be combined so as to further enhance the overall strain obtained in the corresponding channel regions. However, these strain-inducing mechanisms may be considered as “local” mechanisms, since the strain may be induced in and above the corresponding active region for the transistor element under consideration, wherein the finally obtained strain component in the channel region may significantly depend on the overall device dimensions. That is, typically, these local strain-inducing mechanisms may rely on the stress transfer capabilities via other device components, such as gate electrodes, spacer elements formed on sidewalls of the gate electrodes, the lateral dimensions of the drain and source regions and the like. Consequently, the magnitude of the strain in the channel region may significantly depend on the technology under consideration, since, typically, reduced device dimensions may result in an over-proportional reduction of the corresponding strain-inducing mechanism. For example, creating strain by a dielectric overlayer, such as a contact etch stop layer, may frequently be used, wherein, however, the amount of internal stress of the corresponding dielectric material may be restricted by deposition-related constraints while, at the same time, upon reducing device dimensions, for instance the spacing between two neighboring transistor elements, may require a significant reduction of the layer thickness, which may thus result in a reduction of the finally obtained strain component. For these reasons, typically, the magnitude of the strain in the channel region provided by the local strain-inducing mechanisms may be several hundred MPa, while a further increase of this value may be difficult to be achieved upon further device scaling.
For this reason, attention is again increasingly drawn to other mechanisms in which a moderately high degree of strain may be created in a global manner, i.e., on a wafer level, so that the corresponding active regions of the transistor elements may be formed in a globally strained semiconductor material, thereby providing a direct strain component in the corresponding channel regions. For instance, as one of the earliest strain techniques, a silicon material may be epitaxially grown on an appropriately designed buffer layer in order to obtain a strained silicon layer. For example, a silicon/germanium buffer layer which may be provided with its substantially natural lattice constant may be used for forming thereon a strained silicon layer, which may have a moderately high tensile biaxial strain of 1 GPa or higher, depending on the lattice mismatch between the buffer layer and the strained silicon layer. For example, a substantially relaxed silicon/germanium layer having a fraction of approximately 20 atomic percent germanium may result in a tensile biaxial strain of a corresponding epitaxially grown silicon material of 1.3 GPa, which is significantly higher compared to the strain levels obtained by the local strain-inducing mechanisms described above. The global biaxial strain in the silicon results in an increase of the degree of degeneration of the conduction band, thereby creating two sets of sub-valleys with different effective electron masses. An appropriate re-population of the theses energy states thus leads to a higher electron mobility and hence a higher drive current of N-channel transistors.
The creation of a global strained silicon layer may also be efficiently accomplished on the basis of an SOI (silicon-on-insulator) architecture by sophisticated wafer bonding techniques. That is, a strained silicon layer may be formed on the basis of an appropriately designed buffer layer, as explained above, and the corresponding silicon layer may be bonded to a carrier wafer having formed thereon a silicon dioxide layer. After the bonding of the strained silicon layer to the carrier wafer, the strained semiconductor layer may be cleaved, for instance by incorporating an appropriate species, such as hydrogen, helium and the like, wherein the previously generated strain may be substantially maintained due to the adhesion of the strained silicon material on the material of the carrier wafer. Consequently, a globally strained silicon layer may also be provided in applications in which SOI architecture may be required, at least for performance driven transistor elements.
In principle, providing a globally strained semiconductor layer, for instance on the basis of an SOI architecture, may represent a promising approach, since the strain values may be significantly higher compared to local strain-inducing mechanisms. When applying a globally strained silicon-based layer in sophisticated semiconductor devices, it turns out, however, that, upon reducing the overall dimensions of circuit elements, the strain levels in the associated active regions is also reduced, as will be explained in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a perspective view of a semiconductor substrate 101, such as a silicon wafer, which may comprise a base material 102, for instance in the form of silicon and the like, above which is formed a globally strained silicon layer 104, which may also comprise other components, such as dopants and the like, as required for forming sophisticated transistor elements in and above the semiconductor layer 104. Furthermore, as previously discussed, frequently, an SOI architecture is used in advanced semiconductor devices, wherein a buried insulating layer 103, such as a silicon dioxide material, is formed between the base material 102 and the semiconductor layer 104. The semiconductor layer 104 may have a high biaxial strain component, such as a tensile strain, as indicated by 104T, which may have a magnitude of several hundred MPa, or one 1 GPa and higher. As previously discussed, the substrate 101 may be fabricated on the basis of well-established wafer bond techniques, in which the semiconductor layer 104 may be grown on an appropriate crystalline template material having an appropriate crystallographic configuration so as to grow the semiconductor material of the layer 104 with a desired strain. For example, a silicon/germanium material may frequently be used as a template or buffer material, wherein the lattice mismatch between the relaxed silicon/germanium material and the natural lattice constant of a silicon material may result in a tensile strained deposition of the semiconductor material of the layer 104. The desired high tensile strain component may be preserved upon bonding the semiconductor layer 104 to the buried insulating layer 103, thereby obtaining the substrate 101 after removing the material of the template or buffer layer and the corresponding carrier substrate.
FIG. 1b schematically illustrates a cross-sectional view of a portion of the substrate 101. As illustrated, the semiconductor layer 104 with the desired high tensile strain 104T is formed on the buried insulating layer 103. Thus, upon forming sophisticated semiconductor devices on the basis of the substrate 101, the semiconductor layer 104 is to be patterned, for instance, for defining appropriate semiconductor regions or active regions, in and above which circuit elements, such as transistors, are to be formed. Typically, corresponding semiconductor regions are laterally delineated by appropriate isolation structures, such as shallow trench isolations, which, however, may have a significant influence on the resulting strain conditions within the individual active regions.
FIG. 1c schematically illustrates the substrate 101 in a further advanced manufacturing stage. As illustrated, an active region 104A is provided in the semiconductor layer 104, wherein the lateral size and position of the active region 104A is defined by a shallow trench isolation 104C. Hence, the shallow trench isolation 104C laterally delineates the active region 104A, which in turn may be vertically delineated by the buried insulating material 103.
Typically, the substrate 101 as illustrated in FIG. 1c is formed on the basis of the following process techniques. After providing the substrate 101, as for instance shown in FIGS. 1a and 1b, the semiconductor layer 104 may be patterned on the basis of sophisticated lithography techniques in order to form an isolation trench in the layer 104, which corresponds to the trench isolation structure 104C. To this end, any appropriate process strategy may be applied, for instance providing any sacrificial material layers, such as a pad layer, a chemical mechanical polishing (CMP) stop layer and the like, in accordance with the overall process requirements. Next, these optional sacrificial materials may be patterned and may be used for forming appropriate trenches on the basis of a resist mask, which may be accomplished by applying selective plasma-assisted etch recipes. Thus, upon forming an isolation trench, additional surface areas of the semiconductor material in the layer 104 may be created, for instance corresponding sidewall areas 104S are formed which thus represent exposed semiconductor surface areas, at which significantly different strain conditions may occur. That is, upon forming the additional free surface areas 104S, the initial strain component may be significantly reduced, thereby creating a modified strain profile, as indicated by the dashed line 104M, which may represent a boundary within which a moderately high tensile strain may still be preserved, while, within the portion of the active region 104A adjacent to the isolation structure 104C, may have significantly reduced strain components or a substantial relaxed strain condition is generated.
FIGS. 1d-1f schematically illustrate the substrate 101 according to various examples, in which the active region 104A may be formed on the basis of reduced lateral dimensions, at least along a length direction, as indicated by L. For example, in FIG. 1d, a length of the active region 104A may be reduced compared to the active region 104A as shown in FIG. 1c, as may be required in more sophisticated semiconductor devices. Upon reducing the length L of the active region 104A for a given height or thickness, as indicated by H, it turns out that the resulting tensile stress level 104T may further be reduced, while also the strain profile 104M results in an increased area of the active region 104A which may have a non-acceptable reduced strain level or which may even have, for instance, locally at the center, an inverse strain component.
FIG. 1e schematically illustrates the situation for an even further reduced length of the active region 104A, wherein the resulting strain level 104T is further reduced, while at the same time the relaxed areas or areas of inverse strain 104M are even further increased.
FIG. 1f schematically illustrates the situation for a height-to-length aspect ratio of approximately 1, wherein the corresponding strain level 104T may be substantially eliminated so that any performance enhancement may no longer be achieved due to the disadvantageous height-to-length aspect ratio.
Consequently, the patterning of the highly strained semiconductor layer 104 may finally result in the extremely reduced strain component for sophisticated semiconductor devices, which may be caused by the generation of semiconductor islands, in which the fraction of free surface areas with respect to strained surface areas may increase, thereby significantly reducing the efficiency of the corresponding strain-inducing mechanism.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.